Role Overview
We are looking for a Principal Packaging Engineer to own package architecture and development for Velaura’s next-generation SoCs. This role will lead packaging from concept through production, working across silicon, board, system, thermal, mechanical, and manufacturing teams to deliver high-performance, cost-effective, and manufacturable products. The ideal candidate has deep experience with advanced semiconductor packaging, package-level signal and power integrity, substrate and assembly technologies, and cross-functional system optimization.
Responsibilities
● Own package architecture from concept through production for Velaura SoCs.
● Partner with architecture and silicon teams to co-optimize package, die, board, and system design for performance, power, cost, and manufacturability.
● Drive package technology selection, including flip-chip, advanced substrates, fan-out, and future multi-die integration approaches.
●Lead package design, bump planning, substrate definition, escape routing, and assembly interactions with OSAT and substrate vendors.
● Own package-level signal integrity and power integrity planning for high-speed interfaces including LPDDR, PCIe, Ethernet, and other high-speed I/O.
●Collaborate on thermal architecture, mechanical integration, reliability, DFM, and qualification.
●Work with foundry, assembly, substrate, and test partners to successfully deliver products to production.
●Help define Velaura's long-term packaging roadmap as future products evolve.
Required Qualifications
●Deep experience developing advanced semiconductor packages for high-performance SoCs.
●Strong understanding of package architecture, substrate technologies, bumping, assembly flows, and manufacturing.
●Experience co-optimizing package design with silicon, board, SI/PI, thermal, and mechanical teams.
●Hands-on experience with signal integrity, power integrity, thermal, and reliability
considerations in advanced packages.
●Ability to balance technical excellence with cost, yield, manufacturability, and schedule.
●Excellent communication skills and a collaborative, first-principles engineering mindset.
Preferred Qualifications
● Advanced packaging technologies including chiplets, 2.5D integration, silicon bridges, or heterogeneous integration.
● HBM integration and high-bandwidth memory package architecture.
● Advanced process nodes (N3, N2, or beyond).
● Experience working with leading foundries, OSATs, and substrate vendors.
● Experience in an early-stage semiconductor company.
