Role Overview
We are looking for talented RTL Engineers to help build Velaura's next generation Physical AI SoC. You will work closely with architects, performance modelers, software engineers, verification engineers and physical design teams to turn architectural concepts into production silicon.
In this role you will own power management of the SoC at every level, delivering silicon that meets its performance targets well within the power budgets allocated to it.
Responsibilities
Design the on chip power management hardware for the Velaura SoC including digital power meters, activity monitors and throttlers.
Design hardware and software control loops around temperature sensors that hold the die under a defined thermal limit.
Design controls that keep the design under defined activity and average power limits as well as instantaneous di/dt limits.
Work with architects, physical design and package teams on voltage droop behavior, power delivery and adaptive clocking response.
Own clock and reset architecture including clock gating, PLL programming and management, and reset sequencing across power domains.
Define and implement power state management including DVFS, power domains, retention and low power flows.
Correlate power estimates across RTL, emulation and silicon, and build the telemetry that makes power and thermal behavior visible in the field.
Work with firmware and software teams on the interfaces, policies and telemetry that drive power and thermal management.
Required Qualifications
Strong grasp of the physics and electrical engineering behind average power, peak current, thermal behavior and voltage droop, and of how these concepts relate while remaining independent.
Experience designing power management hardware such as digital power meters, throttlers, or thermal and current control loops.
Understanding of di/dt, IR drop and power delivery network behavior, and their impact on timing margin.
Experience with clock and reset architecture including clock gating, PLL management and reset sequencing.
Working knowledge of Verilog or SystemVerilog and modern RTL design methodology.
Experience with power estimation and analysis flows from RTL through gate level.
Strong debugging and problem solving skills across hardware and software boundaries.
BS or higher in Electrical Engineering, Computer Engineering or a related field.
Preferred Qualifications
Experience with DVFS, adaptive voltage scaling, adaptive clocking or droop detection.
Experience with UPF based low power design including power domains, retention and isolation.
Experience correlating pre silicon power models against silicon measurement.
Experience with thermal modeling, sensor placement, or package and board level thermal design.
Experience with firmware or PMIC interfaces and power management software.
Experience with power analysis tools such as PowerArtist, PrimePower or Joules.
Familiarity with robotics, drones, autonomous vehicles or edge AI systems where power and thermal limits are tight.
Experience using AI assisted design workflows to improve productivity and design exploration.
