Role Overview
We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.
This role focuses on our custom CPU. We are designing a leading edge, high performance processor from scratch, and you will own a functional domain of its verification from test plan through coverage closure, proving that a newly designed microarchitecture behaves as intended.
Responsibilities
Own verification of custom CPU units including instruction fetch, decode, load store, and the instruction, data and last level caches.
Work with CPU and SoC architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans.
Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.
Develop instruction level stimulus and compare against a golden instruction set simulator.
Verify memory ordering, coherence, exceptions and privilege behavior against the architecture specification.
Verify latency, bandwidth and cache behavior against high performance targets under representative workloads.
Execute regressions through design and environment bring up, and track progress using bug and coverage metrics.
Support emulation, FPGA prototyping and pre silicon software bring up, and drive root cause analysis across hardware and software boundaries.
Required Qualifications
8 or more years verifying high performance CPUs or complex digital designs.
Strong computer architecture and microarchitecture fundamentals.
Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
Experience owning a block or unit of a design independently from test plan through coverage closure.
Experience writing test plans, portable testbenches and transactors.
Experience debugging complex issues across hardware and software boundaries.
BS or higher in Computer Engineering, Electrical Engineering or Computer Science.
Ability to work effectively in a collaborative multidisciplinary engineering environment.
Preferred Qualifications
Knowledge of the ARM or RISC-V instruction set architecture.
Knowledge of microprocessor verification domains such as cache coherence, memory ordering, prefetching, branch prediction, speculative execution and address translation.
Prior experience verifying front end, fetch, load store, instruction cache, data cache or last level cache units.
Knowledge of vector units or matrix multiplication units.
Experience with random instruction sequencing, formal verification, gate level simulation or silicon bring up.
Experience verifying a custom processor developed from scratch rather than an integrated third party core.
Experience leading a small team of verification engineers.
Experience using AI assisted verification workflows to improve productivity and coverage.
