TECHNOLOGY · FRAMEWORKS & LIBRARIES

Universal Verification Methodology

Standardized SystemVerilog-based framework for functional verification of hardware designs, widely adopted in chip development.

Open roles mentioning it
77
Companies hiring for it
22
Remote share
3%
WHO'S HIRING

Companies with open roles mentioning Universal Verification Methodology

SpaceX13 open rolesAstera Labs12 open rolesTenstorrent10 open rolesBaya Systems5 open rolesEthernovia5 open rolesEliyan5 open rolesCerebras Systems4 open rolesLightmatter3 open rolesAstranis3 open rolesOuster2 open rolesMatX2 open rolesWaymo2 open roles
APPEARS ALONGSIDE

Technologies mentioned in the same job posts

SystemVerilog×51Python×43Verilog×28C++×23Xilinx×9Tcl×8Microsoft Fabric×7MATLAB×6Bash×5Linux×4
COMMON ROLES

Job titles that ask for Universal Verification Methodology

  • Design Verification Engineer (Silicon Engineering)4
  • Design Verification Engineer4
  • Sr. Asic Design Verification Engineer (Silicon Engineering)4
  • Hardware Verification Engineer4
  • Principal Design Verification Engineer (Silicon Engineering)4
  • Senior Asic Design Verification Engineer3
  • Fpga Manager2
  • Principal Design Verification Engineer2
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