Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at .
Role Overview
Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a Staff DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.
Key Responsibilities
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DFT Architecture & Strategy
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Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
- Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
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DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies
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Test Pattern Development & Optimization
- Generate and optimize high-quality test and debug patterns for production
- Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
- Drive test coverage and quality metrics to meet stringent manufacturing requirements
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Cross-Functional Collaboration & Methodology Innovation
- Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
- Participate in developing and maintaining cutting-edge DFT implementation flows
- Automate and improve methodologies using advanced scripting and tools
Basic Qualifications
Preferred Qualifications
- Master's degree in Electrical Engineering or related field
- Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements
- Experience in chip bring-up and mass production activities
- Background in advanced process technologies (7nm and below)
- Excellent communication skills with ability to work effectively in global team environments
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
