Role Overview
We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.
This role focuses on system level verification. The scope spans boot and root of trust, clock and reset topology, low power behavior, and the IO and memory subsystems that carry real traffic. You will work in one or more of these areas, matched to your strengths and to program needs, and carry that work through sign off and into tape out.
Responsibilities
Drive verification planning and execution for your assigned areas of the Velaura Physical AI SoC.
Build and maintain SoC level simulation environments and flows for CPU based SoCs such as ARM or RISC-V.
Verify boot flows, root of trust, security state transitions and firmware handoff.
Verify clock and reset topology, power domains and low power behavior at system level.
Verify IO and memory subsystem integration including PCIe and LPDDR.
Run CDC and RDC analysis at SoC level and close findings with the design teams.
Verify system level latency, bandwidth and QoS under representative workloads.
Support SoC sign off criteria, coverage closure and tape out readiness.
Required Qualifications
10 or more years in design verification, including significant SoC level experience.
Experience leading or participating in multiple SoC verification projects, including sign off and tape out.
Experience with SystemVerilog, UVM, C and C++ and coverage driven verification at system level.
Experience managing simulation flows on CPU based SoCs such as ARM or RISC-V.
Knowledge of IO and memory subsystem IP such as PCIe and LPDDR5 or LPDDR6.
Experience verifying boot sequences and root of trust.
Experience verifying clock and reset topology at system level, with hands on use of CDC and RDC tools.
Experience with low power verification tools and UPF based flows.
Preferred Qualifications
Depth in one or more areas such as security, memory subsystem, interconnect or power management.
Experience with HW and SW co verification and pre silicon software bring up.
Experience with emulation and FPGA prototyping at SoC level.
Experience with one or more of ISO 26262, IEC 61508, IEC 61511 or ISO 13849.
Experience verifying QoS, latency sensitive or real time systems.
Experience with post silicon bring up, debug and root cause analysis.
Familiarity with robotics, drones, autonomous vehicles or industrial automation systems.
Experience using AI assisted verification workflows to improve productivity and coverage.
